In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature sizes of integrated circuits (ICs) are continuously reduced. In order to accommodate the reduction of the feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) may be reduced accordingly. However, as the channel length of the devices is reduced, the distance between the source and the drain of the devices is also reduced. Therefore, the ability of the gate in controlling the channel may be deteriorated, and thus pinching off the channel by the gate may become more and more difficult. As such, the sub-threshold leakage phenomenon, i.e. the short-channel effect (SCE), may more easily take place.
Therefore, to better accommodate the reduction of the feature size, the semiconductor process gradually switches from planar MOSFET devices to more efficient three-dimensional (3D) transistor devices, such as fin field-effect transistors (Fin-FETs). In a Fin-FET, the gate may be able to control an ultra-thin structure (i.e., a fin structure) from at least two side surfaces. As compared to a planar MOSFET device, the gate in a Fin-FET may demonstrate stronger ability in controlling the channel, and thus the SCE may be suppressed. In addition, as compared to other devices, Fin-FETs have better compatibility with the existing IC manufacturing.
However, the electrical performance of the conventional semiconductor structures may still need to be improved. The disclosed semiconductor structures and fabrication methods are directed to solve one or more problems set forth above and other problems in the art.